The present invention relates to the field of data communications and more particularly relates to a self-compensating glitch free clock switch mechanism.
Many communication systems today, such as the Bluetooth standard, are implemented in a master/slave arrangement whereby several slave communication devices communicate with a master communication device. These systems are often designed as isochronous or synchronous communication systems. A problem often encountered by such systems is how to synchronize the master/slave communications channel. In a Time Division Multiples Access (TDMA) system, slave devices are configured to xe2x80x98sleepxe2x80x99 during the time they are not actively communicating with the master (or base) communication device. Low power consumption, an increasingly important goal, is achieved by employing two clocks. A fast clock is used during data transmission with the master and a slow clock is used for the remainder of the time. Thus, the problem of synchronization between master and slave devices is particularly challenging due to the use of a multi-clock scheme.
Counters are typically used to track the time when a slave device is to awaken for transmission. After transmission is complete (i.e. active cycle finishes) the slave device goes to sleep and the clock switches from fast to slow in order to minimize power consumption. Interrupts are configured to wake the slave up at the next transmission time. When transitioning from fast clock to slow clock, however, synchronization between the master and slave devices is lost due to the ambiguity created during the switching event.
The ambiguity problem arises during the switching from fast to slow domains wherein the first cycle of the slow clock is ambiguous and unpredicted. The actual amount of ambiguity depends only on the phase relation between the fast and slow clocks. The metastability of the first cycle of the slow clock after switching can therefore be a maximum of up to one period of the slow clock and results in unpredicted timing drift over time. Since both fast and slow clocks are separate free running clocks, the switching from one to the other occurs at arbitrary instances in time. Worst case is that the slow clock is off an entire slow clock period. The maximum ambiguity of a slow to fast clock transition is the period of a fast clock cycle.
For example, consider a fast clock of 1 MHz and a slow clock of 32 kHz. One cycle of the slow clock is therefore approximately 30 microseconds. The maximum ambiguity is this system is therefore 30 microseconds that may or may not be tolerable depending on the required accuracy. In a system that requires +/xe2x88x9210 microseconds accuracy, 30 microseconds ambiguity is non acceptable.
Using a multiplexer alone to switch the clock is not sufficient because of the restriction on the width of the glitch. The glitch may be sufficient to lock up any flip-flops in the circuit.
An example timing diagram illustrating the uncertainty of the first slow clock cycle during fast to slow clock switching is shown in FIG. 1. The signals shown in the example timing diagram include the fast clock, slow clock, switch enable signal and the frame counter clock which is used to determine when the slave device is to wake up and go to sleep. As indicated, the first slow clock cycle can be off by up to an entire slow clock period.
A diagram illustrating the resultant frame counter drift due to fast to slow and slow to fast clock switching is shown in FIG. 2. The uncertainty generated during fast to slow and slow to fast clock switching is caused by the slave losing synchronization achieved during the previous synchronization event. The loss in synchronization is caused by the unpredictable phase shift between the fast and slow clock during clock switching of the frame counter.
There is therefore a need for a clock switching mechanism that is capable of providing glitch free switching between two clocks. In addition, the mechanism should be self-correcting whereby the ambiguity created during the first slow clock period is compensated for.
The present invention is a glitch free self-correcting clock switching mechanism operative to switch between two clocks in a glitch free manner while compensating for the ambiguity inherent in the switching operation itself. The mechanism of the present invention is especially suited for use in communication systems that employ a master/slave configuration. In particular, the invention is suited for use in slave communication devices to perform the clock switching that occurs in transitioning between active and sleep modes of operation.
During the switching from fast to slow clock domains the mechanism of the present invention measures the uncertainty or ambiguity of the first slow clock cycle duration during the switching operation and stores this value. During the slow to fast clock switching the clock switch mechanism compensates for the metastability of the first slow clock cycle during fast to slow switching using the ambiguity value previously measured. In this manner the fast and slow clocks are switched from one to the other in a glitch-free and self compensating manner. Note that the resolution of compensation of the clock switch is up to one fast clock cycle. In addition, the slow to fast switching request command must be received one full cycle before the actual desired point of switching.
One advantage of the clock switch of the present invention is that the timing drift caused by switching between fast and slow clock domains is compensated for within the switch itself The mechanism can be applied for use in many types of systems and is a general solution that frees system resources that would otherwise be consumed in handling the drift compensation caused by fast to slow clock switching. It is noted that the system resources used must be of a real-time nature since the drift compensation task itself occurs in real-time.
Note that many aspects of the invention described herein may be constructed as software objects that are executed in embedded devices as firmware, software objects that are executed as part of a software application on either an embedded or non-embedded computer system running a real-time operating system such as WinCE, Symbian, OSE, Embedded LINUX, etc. or non-real time operating system such as Windows, UNIX, LINUX, etc., or as soft core realized HDL circuits embodied in an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA), or as functionally equivalent discrete hardware components.
There is thus provided in accordance with the invention, a method of switching between a first clock and a second clock, the second clock having a slower rate than that of the first clock, the method comprising the steps of receiving a first switch command signal to switch from the first clock to the second clock, generating a first mask signal so as to mask the first clock until a next positive transition of the second clock, measuring a first time duration the first mask signal was active to determine the ambiguity of a first cycle of the second clock, outputting the second clock as an output clock, receiving a second switch command signal to switch from the second clock to the first clock, generating a second mask signal having a second time duration of one second clock period less the first time duration to mask the second clock so as to compensate for the ambiguity of the first cycle of the second clock and outputting the first clock as the output clock.
There is also provided in accordance with the invention, a method of switching between a fast clock and a slow clock, the fast clock having a higher clock rate than that of the slow clock, the method comprising the steps of providing a counter loaded initially with a value corresponding to a period of the slow clock, receiving a first command to switch from the fast clock to the slow clock, in response to the first command, generating a first mask signal until a first low to high transition of the slow clock for masking the fast clock, enabling count down of the counter while the mask signal is active and freezing the counter thereafter, switching from the fast clock to the slow clock, receiving a second command to switch from the slow clock to the fast clock, in response to the second command, enabling the countdown of the counter to zero, generating a second mask signal until the counter reaches zero and switching from the slow clock to the fast clock.
There is further provided in accordance with the invention, a method of switching between a fast clock and a slow clock, the fast clock having a higher clock rate than that of the slow clock, the method comprising the steps of receiving a first command to switch from the fast clock to the slow clock, switching from the fast clock to the slow clock, measuring the ambiguity of a first slow clock cycle, receiving a second command to switch from the slow clock to the fast clock, compensating the last cycle of the slow clock by an amount corresponding to the previously measured ambiguity and switching from the slow clock to the fast clock.
There is also provided in accordance with the invention, a clock switching apparatus comprising a multiplexer for switching between a slow clock and a fast clock input thereto, a gate for gating the output of the multiplexer with a mask signal, the gate adapted to produce an output clock signal, a counter adapted to count down a period of the slow clock, a timing and control circuit adapted to receive a first command to switch from the fast clock to the slow clock, in response to the first command, first activate the mask signal until a first low to high transition of the slow clock, enable countdown of the counter while the mask signal is active and freezing the counter thereafter, configure the multiplexer to output the slow clock, receive a second command to switch from the slow clock to the fast clock, in response to the second command, enable the countdown of the counter to zero, second activate the mask signal until the counter reaches zero and configure the multiplexer to output the fast clock.